This invention relates to equalization methods and circuits for data communication. Methods and circuits are presented to improve the performance of equalization circuits at high data-rates.
Equalization circuitry is used to extract a data signal from a received signal. The received signal may be of poor quality because of frequency dependent attenuation causing inter-symbol interference (ISI), and because of other attenuation and noise that may be received with the signal. The received signal may also contain attenuation and noise introduced by the transmission and receiving circuitry and by the transmission media the signal was transmitted on. Accurately extracting the data signal from the received signal requires distinguishing the data signal from the ISI and noise signals received. Accurately extracting the transmitted data signal may be especially difficult in high-speed applications in which signal spread caused by ISI and timing errors in transmission or receiving circuitry may adversely affect the extraction of the data signal.
Feed-forward equalization (FFE) circuits and decision feedback equalization (DFE) circuits are commonly used to extract the data signal from the received signal. FFE circuits may be analog or digital circuits. DFE circuits generally include clocked digital circuits in their feedback loop. In order to improve the performance of equalization circuits, FFE and DFE circuits are generally used in combination.
In high-speed applications in which the data signal has a high data-rate, the FFE and DFE equalization circuits must be capable of operation at the high signal data-rate. However, the performance of known FFE and DFE circuits generally decreases at very high data-rates because of circuit parasitics, circuit loading, and noise.
It is an object of the present invention to provide improved equalization circuitry for use in high-speed, high data-rate applications.